Technical Field
The present invention relates to semiconductor processing, and more particularly to semiconductor devices and methods for fabrication having an airgap protection layer for via placement and alignment.
Description of the Related Art
Current integration schemes for airgap processing require that no gaps are formed around vias landing on a metal level that is gapped. In dense circuit structures, this restriction can significantly limit the area that is able to be gapped. Additionally, the gaps are placed on consecutive levels, and the risk that the gaps will merge and cause significant defectivity exists. Further, wide lines or other structures etched deeper than standard lines can encroach on an airgap therebelow, which can lead to shorts or other defectivity problems. Protecting the metal lines during the formation of an airgap does not presently include a way to specifically protect the airgap from either the via landing on the metal or from the airgap or metal line above.